| Manufacturer | Hitachi Displays, Ltd. |
| Model number | TX26D60VC1CAA |
| Resolution | 640 x 480 pixels (VGA) |
| Stripe organization | R,G,B |
| Color depth | 6 bit per channel, approx. 256 thousands of colors |
| Source | a broken AST Ascentia 910N |
Update 07/29: The connector is called Hirose DF9. I believe it should be a DF9B-31P-1V. The matching connector should be DF9-31S-1V. Other similar connectors (e.g., JAE made this type of connectors too, and has its own number) are possible too. (Serina)
The interface itself has 31 pins in two lines (16+15):
| Pin | Signal | Description |
|---|---|---|
| 1 | Vss | |
| 2 | DCLK | Dot clock |
| 3 | HSYNC | Horizontal synchronization |
| 4 | VSYNC | Vertical synchronization |
| 5 | Vss | |
| 6 | R0 | Red data, LSB |
| 7 | R1 | Red data |
| 8 | R2 | Red data |
| 9 | R3 | Red data |
| 10 | R4 | Red data |
| 11 | R5 | Red data, MSB |
| 12 | Vss | |
| 13 | G0 | Green data, LSB |
| 14 | G1 | Green data |
| 15 | G2 | Green data |
| 16 | G3 | Green data |
| 17 | G4 | Green data |
| 18 | G5 | Green data, MSB |
| 19 | Vss | |
| 20 | B0 | Blue data, LSB |
| 21 | B1 | Blue data |
| 22 | B2 | Blue data |
| 23 | B3 | Blue data |
| 24 | B4 | Blue data |
| 25 | B5 | Blue data, MSB |
| 26 | Vss | |
| 27 | DTMG | Data timing |
| 28 | Vdd | |
| 29 | Vdd | |
| 30 | Vdd | |
| 31 | NC | Leave unconnected, could be TEST signal |
The following cable was used in the AST Ascentia 910N laptop:
If we separate the cable ending into two parts, let's say A and B, then A will have 26 wires and the B part 20 wires. Signal assignment was reverse engineered from the laptop's mainboard and the datasheet of the graphic controller. Measuring the unknown wires (other than ground and power) lead to these results:
| Pin | Part A | Part B |
|---|---|---|
| 1 | Detection loop | Vss |
| 2 | Vss | G5 |
| 3 | Vss | G4 |
| 4 | Detection loop | R5 |
| 5 | Detection loop | R4 |
| 6 | Vss | Vss |
| 7 | Vss | B5 |
| 8 | Vdd | HSYNC |
| 9 | Vdd | DTMG |
| 10 | R3 | VSYNC |
| 11 | R2 | B4 |
| 12 | R1 | N.C. |
| 13 | R0 | Unknown backlit signal |
| 14 | Vss | Vss |
| 15 | G3 | Vss |
| 16 | G2 | Vss |
| 17 | G1 | Backlit on/off |
| 18 | G0 | Backlit power |
| 19 | Vss | Backlit power |
| 20 | B3 | Backlit power |
| 21 | B2 | - |
| 22 | B1 | - |
| 23 | B0 | - |
| 24 | Vss | - |
| 25 | DCLK | - |
| 26 | Vss | - |
The similar module (TX26D01VM1CAA) described in an available datasheet (link on the end) has a Vdd=3.3V, but my meauserements on the AST laptop indicated a 5V voltage on the Vdd signal, so in the testing application I used also a 5V source and it worked (during few hours of testing, when I will be able to get a regulated supply, I make additional tests to find out whenever is the module able to run on 3.3V).
Update 07/29: This module should also run at 3.3V, if I'm not mistaken. (Serina)
The backlit inverter was originally powered by 15.5 - 16 V DC from the AC adapter (at least when the laptop run on AC, I did not get it to run from battery) however it was working also on 12V DC.
Backlit on/off signal is specified as a TTL signal, but in the testing application i've simply connected it to te backlit power pin. There is also one unknown signal from or to the backlit unit, I haven't discovered yet what it can be, maybe an intensity control signal.
Update 07/29: Inverters usually take two types of signals, brightness control and on/off. Different voltage through BRT control results in different brightness. (Serina)
TODO: further testing needed on brightness control. When it will work, a simple D/A converter from resistors should be enougn, e.g. 4 bit for 16 brightness levels. (I'll put here some info in few days/weeks I hope)
The timing diagram is based on the timing of a similar module, namely TX26D01VM1CAA.
Update 08/04: The parameters of the timing are quite the same as written in VESA Safe Mode Timing standard, only in Vsync, the 34 and 35 are the values which differs, but maybe only because of interpretation problems.
| Parameter | Name | Value | Unit | ||
|---|---|---|---|---|---|
| minimal | normal | maximal | |||
| tDCLK | Dot clock period | 40 | ns | ||
| tHP | Horizontal period | 785 | 800 | tDCLK | |
| tHBP | Horizontal back-porch | 144 | |||
| tHFP | Horizontal front-porch | 1 | 16 | ||
| tWH | Horizontal active width | 96 | |||
| tVP | Vertical period | 515 | 525 | tHP | |
| tVBP | Vertical back-porch | 34 | |||
| tVFP | Vertical front-porch | 1 | 11 | ||
| tVW | Vertical active width | 4 | |||
The functionality of the module and the proper timing values were verified using the following wiring to the parallel port a PC:
| TFT signal | TFT pin | LPT pin | LPT signal | Power suppy |
|---|---|---|---|---|
| DCLK | 2 | 2 | D0 | - |
| DTMG | 27 | 3 | D1 | |
| HSYNC | 3 | 4 | D2 | |
| VSYNC | 4 | 5 | D3 | |
| R0-5 | 6-11 | 6 | D4 | |
| G0-5 | 13-18 | 7 | D5 | |
| B0-5 | 20-25 | 8 | D6 | |
| Vss | 1, 5, 12, 19, 26 | 18-25 | GND | GND |
| Vdd | 28, 29, 30 | - | - | +5V |
You can download my driver and the following stripes test patter program - tx26d60vc1caa.tar.bz2.
The display is also able to show nice bitmaps:
Now, when I know that the panel is working, there are several ways to continue:
If you feel that you can help me with realizing one of them, please contact me.