//
    //  Synchronization signal generator
    //
    //  by Daniel Rozsnyo <daniel@rozsnyo.com>
    //
    
    module sync_gen( 
        inClock, 
        inReset,
        inData, inAddr, inWrite, 
        outCounter, 
        outActive, outSync, 
    );

    
    // -------------------------------------------------- interface
    
    // inputs
    input        inClock;               // LH step, HL outbuff
    input        inReset;               // asynchronous, active H
    input[11:0]  inData;                
    input[1:0]   inAddr;
    input        inWrite;               // #WE signal, active L
    
    // outputs
    output[11:0] outCounter;
    output       outActive;             // active H in state0
    output       outSync;               // active L in state2
    
    
    // -------------------------------------------------- internal state

    // timing settings
    reg [11:0]  cfgActive;
    reg [11:0]  cfgFront;
    reg [11:0]  cfgSync;
    reg [11:0]  cfgBack;
    
    // internal counters
    reg [11:0]  cntPosition;
    reg [1:0]   cntState;
    
    // output buffers
    reg [11:0]  outCounter;
    reg         outActive;         
    reg         outSync;           
    

    // -------------------------------------------------- internal signals
    
    reg         intLast;
    
    
    // -------------------------------------------------- loading of config registers
    
    always @( inAddr or inWrite ) begin
    
        if ( !inWrite ) begin
            case( inAddr )
                0 : cfgActive = inData;
                1 : cfgFront  = inData;
                2 : cfgSync   = inData;
                3 : cfgBack   = inData;
            endcase
        end
        
    end

    
    // -------------------------------------------------- combinatorial internal signals
    
    always @( cntPosition or cntState ) begin
        case( cntState )
            0 : intLast = cntPosition == cfgActive;
            1 : intLast = cntPosition == cfgFront;
            2 : intLast = cntPosition == cfgSync;
            3 : intLast = cntPosition == cfgBack;
        endcase
    end


    // -------------------------------------------------- asynchronous reset signal
    
    always @( inReset ) begin
    
        if ( inReset ) begin
            cntPosition = 0;
            cntState    = 0;
        end
        
    end
    
    
    // -------------------------------------------------- making an iteration
    
    always @( posedge inClock ) begin
    
        cntPosition <= cntPosition + 1;

        if ( intLast ) begin
            cntState    <= cntState + 1;
        end
    
        if (( intLast & (cntState==3) ) | inReset ) begin
            cntState    <= 0;
            cntPosition <= 0;
        end
        
    end
    

    // -------------------------------------------------- buffered output signals
    
    always @( negedge inClock ) begin

        outCounter <= cntPosition;
        outActive  <= cntState == 0;
        outSync    <= cntState != 2;
        
    end
    

    endmodule