Synchronization signal generator
My first Verilog module is a programmable synchronization signal generator
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Files:
syncgen.v
3.0 KB
syncgen_test.v
1.7 KB
runall.sh
281 B
syncgen_scheme.png
1024 × 768, 30.0 KB
syncgen_output.png
1049 × 418, 34.5 KB
syncgen.tar.bz2
2.7 KB