//
    //  H/V Synchronization signal generator TEST MODULE
    //
    //  by Daniel Rozsnyo <daniel@rozsnyo.com>
    //

    module sync_gen_2d_test();


        reg         iCLOCK;
        reg         iRESET;
        reg[11:0]   iDATA;
        reg[2:0]    iADDRESS;
        reg         iWRITE;


        wire[11:0]  oPOSX;
        wire[11:0]  oPOSY;
        wire        oACTIVE;
        wire        oHSYNC;
        wire        oVSYNC;


        sync_gen_2d sg2d(
            .inClock            (iCLOCK),
            .inReset            (iRESET),
            .inData             (iDATA), 
            .inAddr             (iADDRESS), 
            .inWrite            (iWRITE),
            .outX               (oPOSX),
            .outY               (oPOSY),
            .outActive          (oACTIVE), 
            .outHSync           (oHSYNC),
            .outVSync           (oVSYNC)
        );


        initial begin
        
           $dumpfile( "syncgen_2d_test.vcd" );
           $dumpvars;
        
           iRESET = 1;
           iWRITE = 1;
        
           config_set( 0,  7 );
           config_set( 1, 10 );
           config_set( 2, 12 );
           config_set( 3, 16 );
      
           config_set( 4,  3 );
           config_set( 5,  6 );
           config_set( 6,  8 );
           config_set( 7, 12 );
           
//           # 640x480 @ 60.00 Hz (GTF) hsync: 29.82 kHz; pclk: 23.86 MHz
//           Modeline "640x480_60.00"  23.86  640 656 720 800  480 481 484 497  -HSync +Vsync
  
//           config_set( 0, 639 );
//           config_set( 1, 655 );
//           config_set( 2, 719 );
//           config_set( 3, 799 );
        
//           config_set( 4, 479 );
//           config_set( 5, 480 );
//           config_set( 6, 483 );
//           config_set( 7, 496 );

           #15
           iRESET = 0;
        
//           #8000000;
           #10000;
           $finish;
        
        end
        
        
        initial begin
        
            iCLOCK = 1;
        
            forever begin
                #10;
                iCLOCK = !iCLOCK;
            end
        
        end
        
        
        task config_set;
            input [2:0] a;
            input [11:0] d;
        begin
        
            #10
            iDATA    = d;
            iADDRESS = a;
            
            #10
            iWRITE   = 0;
            #10
            iWRITE   = 1;
            
        end
        endtask
        
        
    endmodule