//
    //  Synchronization signal generator TEST MODULE
    //
    //  by Daniel Rozsnyo <daniel@rozsnyo.com>
    //

    module sync_gen_test();


        reg         iCLOCK;
        reg         iRESET;
        reg[11:0]   iDATA;
        reg[1:0]    iADDRESS;
        reg         iWRITE;


        wire[11:0]  oCOUNTER;
        wire        oACTIVE;
        wire        oSYNC;


        sync_gen sg(
            .inClock            (iCLOCK),
            .inReset            (iRESET),
            .inData             (iDATA), 
            .inAddr             (iADDRESS), 
            .inWrite            (iWRITE),
            .outCounter         (oCOUNTER),
            .outActive          (oACTIVE), 
            .outSync            (oSYNC)
        );


        initial begin
        
           $dumpfile( "syncgen_test.vcd" );
           $dumpvars;
        
           iRESET = 1;
           iWRITE = 1;
        
           config_set( 0,  7 );
           config_set( 1, 10 );
           config_set( 2, 12 );
           config_set( 3, 16 );
        
           #15
           iRESET = 0;
        
           #2000;
           $finish;
        
        end
        
        
        initial begin
        
            iCLOCK = 1;
        
            forever begin
                #10;
                iCLOCK = !iCLOCK;
            end
        
        end
        
        
        task config_set;
        input [1:0] a;
        input [11:0] d;
        begin
        
            #10
            iDATA    = d;
            iADDRESS = a;
            
            #10
            iWRITE   = 0;
            #10
            iWRITE   = 1;
            
        end
        endtask
        
        
    endmodule